Objective Conventional OPA chips require electrical connection to an interposer circuit board via wire bonding, which is then connected to the control circuit system using flexible flat cables. However, large-scale OPA transceiver modules have a vast number of control electrodes, necessitating a huge number of wire bonds. This imposes high requirements on mechanical stability and fabrication precision. Moreover, traditional edge-based layouts make it difficult to achieve compact arrangement of large-scale transceiver modules and waste valuable wafer area resources. By leveraging Through-Silicon Via (TSV) technology, the precious wafer area can be fully utilized, significantly improving the integration density, mechanical stability, and energy efficiency of photonic chips. Additionally, a limiting bottleneck in the practical application of OPA chips is the large beam divergence angle caused by their small antenna aperture. The traditional solution is to continuously increase the size of the phased array. As the number of pins increases and integration density rises, the packaging requirements for integrated photonic chips become increasingly stringent, and the difficulty of wire bonding increases exponentially. By employing Ball Grid Array (BGA) packaging technology, it is possible to increase the number of pins and spacing while simultaneously resolving coplanarity and warpage issues caused by wires in fine-pitch devices, thereby meeting the demands of performance enhancement in silicon-based integrated OPA chips.

Methods This research utilizes microelectronics methodologies, employing TSV technology to achieve vertical interconnections between the electrode control chip and the silicon interposer, as well as between the phase control electrodes in the OPA chip and the silicon interposer. The electrode control chip and the phase control electrodes in the OPA chip are electrically interconnected via metal routing on the PCB. BGA packaging technology is used to establish both electrical and mechanical connections between the silicon interposer and the PCB. By adopting co-packaging of electronics and photonics, the interconnect length is shortened, the chip size is reduced, thereby minimizing parasitic effects, enhancing integration density, and reducing power consumption. Through practical experiments, the two critical technologies from integrated circuits—TSV interconnection and BGA packaging—have been successfully transplanted and functionally realized in OPA chips. The effectiveness and feasibility of the proposed method have been verified through OPA module packaging experiments and OPA field-of-view scanning experiments. The results indicate that this research meets the design requirements for the fabrication of optical phased array transceiver modules and the performance testing of optical phased array field-of-view scanning. It solves the packaging difficulties associated with small-sized, large-scale OPA chips, further improves on-chip integration density, and provides new insights for fully leveraging the miniaturized integration advantages of optical phased array chips.

Results and Discussions The paper first establishes the feasibility of this innovative design through theoretical analysis. Subsequently, the experimental design proceeds in two directions: the fabrication of the OPA chip transceiver module and the validation of the OPA transceiver module's field-of-view scanning performance. Regarding the fabrication of the OPA chip transceiver module, microscope observation was used to verify the following parameters: waveguide array scale ≥128, photonics chip via diameter ≤80 μm, photonics chip via count ≥256 (Tab.1), with all relevant technical specifications being achievable. For the validation of the OPA chip transceiver module's field-of-view scanning performance, methods involving the construction of an infrared imaging experimental setup and data analysis confirmed the following: phased array scanning range ≥50°, wavelength-tuning scanning range ≥15°, vertical beam divergence angle ≤0.5°, horizontal beam divergence angle ≤0.5° (Tab.2), with all relevant technical specifications being achievable.

Conclusions The OPA chip transceiver module based on TSV interconnection and BGA packaging can essentially reach the level of engineering application. By leveraging the advantages of integrated packaging in the field of electronic chips, this research solves the packaging challenges of small-sized, large-scale OPA chips, further enhances on-chip integration density, and provides technical guidance and new ideas for researchers in the field of OPA transceiver module integrated packaging.