[1] |
Tang S J, Song M M, Wang B Y, et al. Infrared scene generation technology based on hardware-in-the-loop simulation of MOS resistance arrays [J]. Journal of System Simulation, 2018, 30(4): 1319-1327. (in Chinese) |
[2] |
Lv J, Kong W H, Li J. Development analysis of foreign tactical missile hardware-in-the-loop simulation capability [J]. Tactical Missile Technology, 2020, 2: 99-104. |
[3] |
Huang R S, Li H F, Liu G, et al. Status and development analysis of hardware-in-the-loop simulation technologies for the aircraft [J]. Journal of System Simulation, 2019, 31(9): 1763-1774. |
[4] |
Chen H Y, Zhao S Q, Wu G S, et al. Research on dual-band infrared image generation technology based on MOS resistor array [J]. Air & Space Defense, 2020, 3(4): 96-102. (in Chinese) |
[5] |
Gan Z H, Wu M, Zhu J K, et al. Research on a pulse tube cooler for resistor array cooling [J]. Cryogenics, 2015, 1: 1-7. |
[6] |
Lassiter T L, Marks J, Dickason J, et al. Modular carrier board and package for infrared LED arrays [J]. IEEE Photonics Journal, 2019, 11(4): 6. |
[7] |
Bryant P, Oleson J, James J, et al. MIRAGE: Developments in IRSP system development, RIIC design, emitter fabrication, and performance [C]//SPIE: Technologies for Synthetic Environ-ments: Hardware in the Loop Testing IX, 2004, 5408: 173-187. |
[8] |
James J, Bryant P, Solomon S, et al. OASIS: Cryogenically-optimized resistive arrays & IRSP subsystems for space-background IR simulation [C]//SPIE: Technologies for Synthetic Environments: Hardware-in the-Loop Testing XI, 2006, 6208: 20812. |
[9] |
Zhang W T, Chen X, Ye Z H. Stress in HgCdTe large infrared focal plane array detector analyzed with finite element analysis [J]. Journal of Infrared and Millimeter Waves, 2021, 40(3): 308-313. (in Chinese) |
[10] |
Yuan Q H, Jing H Q, Zhong L, et al. Thermal stress in high-power semiconductor laser packaging [J]. Chinese Journal of Lasers, 2019, 46(10): 1001009. (in Chinese) |
[11] |
Song M M, Tang S J, Wang B Y, et al. Infrared decoy simulation based on MOS resistance array [J]. Infrared and Laser Engineering, 2017, 46(5): 0504002. (in Chinese) |
[12] |
Ma B, Cheng Z X, Zhou H M, et al. Development of domestic resistive arrays technology [J]. Infrared and Laser Engineering, 2011, 40(12): 2314-2322. (in Chinese) |
[13] |
McHugh S, Franks G, LaVeigne J. High-temperature MIRAGE XL (LFRA) IRSP system development [C]//SPIE: Infrared Imaging Systems: Design, Analysis, Modeling, and Testing XXVIII, 2017, 10178: 1017809. |
[14] |
Danielson T, Franks G, Holmes N, et al. Achieving ultra-high temperatures with a resistive emitter array [C]//SPIE: Infrared Imaging Systems: Design, Analysis, Modeling, and Testing XXVII, 2016, 9820: 98200Z. |
[15] |
Zhou S, Liu W G, Cai C L, et al. Development and simulation of the microbridge structure of the resistance array infrared scene generator [J]. Journal of Xi’an Technological University, 2012, 32(8): 613-616. (in Chinese) |
[16] |
Williams O M, Goldsmith G C, Stockbridge R G. History of resistor array infrared projectors: Hindsight is always 100% operability [C]//SPIE: Technologies for Synthetic Environments: Hardware in the Loop Testing X, 2005, 5785: 208-224. |
[17] |
Zhang K, Ma B, Huang Y, et al. Testing and analysing of 256×256 MOS resistor array for IR scene projector [C]//15th International Conference on Advanced Communications Technology (ICACT), 2013: 143-147. |