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图1为FCG跨阻放大电路,虚线框内是光电二极管电路模型,由电流源Iin和结电容Cpd组成。FCG跨阻放大电路的输入阻抗为:
$$ {Z_{in}} \approx \frac{1}{{{g_{m1}}(1 + {g_{m2}}{g_{m3}}{R_2}{R_3})}} $$ (1) 式中:gm为晶体管的跨导。相比于RGC跨阻放大电路和共源放大电路,FCG跨阻放大电路的输入阻抗更小[12]。 M2管和R2组成的共栅放大电路跨接在结点IN和结点X之间,共栅放大电路具有很低的输入阻抗和很大的工作带宽 [16],为M3管的正常工作提供了足够的栅压。然而,结点Y的M3管和电阻R3以及结点O的M1管和电阻R1构成的两级共源放大电路,虽然它们为FCG跨阻放大电路提供了主要的增益,但是在结点X与结点Y之间和结点Y与结点O之间的晶体管寄生电容,分别与R1和R3产生极点,构成了两级低通滤波电路,极大限制了FCG跨阻放大电路的带宽。
因此提出使用CMOS有源电感代替电阻,与FCG跨阻放大电路的共源放大级并联,利用CMOS有源电感的电感特性抵消共源放大电路中寄生电容带来的带宽限制,从而提升整体FCG跨阻放大电路的带宽。
CMOS有源电感和平面螺旋电感类似,在一定频率范围内,阻抗随频率上升,但是CMOS有源电感占用的版图面积比平面螺旋电感小得多,常用于高速光电集成电路的带宽扩展[17]。如图2(a)所示,CMOS有源电感结构仅由一个NMOS晶体管M0和一个电阻Rs组成,图2(b)为CMOS有源电感的小信号模型。
根据图2(b)CMOS有源电感的小信号模型可计算得CMOS有源电感的输出阻抗为:
$$ {Z_{out}} = \frac{{{V_A}}}{{{I_A}}} = \frac{1}{{{g_{m0}}}}\frac{{1 + s{R_s}{C_{gs0}}}}{{1 + s{C_{gs0}}\dfrac{1}{{{g_{m0}}}}}}{\text{ }} $$ (2) 式中:VA和IA是图2(b)中结点A的电压和电流,其中Cgs0是晶体管M1的栅源电容。由输出阻抗函数公式(2)可计算得到,低频时,输出阻抗为1/gm0,高频时,因为Cgs0短路所以输出阻抗等于Rs。CMOS有源电感的频率范围从ωL_z = 1/RsCgs0~ωL_p = gm0/Cgs0,为了更好地实现电感,所以必须满足Rs >> 1/gm0。根据上述CMOS有源电感的特性,可得到等效电感电路如图2(c)所示,其中RL1 = Rs,RL2 = 1/gm0,L ≈ RsCgs0/gm0。
CMOS有源电感改进FCG跨阻放大电路实现带宽扩展的原理如图3所示,图3(a)为采用负载电阻R的共源放大电路,电路中的CL是负载电容,其中包含与下一级之间的寄生电容。图3(b)为采用CMOS有源电感替换电阻负载R后的共源放大电路,图中虚线框内为CMOS有源电感。
图 3 不同负载的共源放大电路原理图
Figure 3. Schematic diagram of common source amplifier circuit for different loads
图3(a)采用电阻负载的共源放大电路的传输函数为:
$$ \frac{{{V_{out}}}}{{{V_{in}}}}(s) = {{ - }}\frac{{{g_m}R}}{{sR{C_L}{{ + }}1}} $$ (3) 由此可以看到和前文所述一致,负载电容CL与电阻R构成了一个低通滤波电路,产生一个极点ωcs_p0 = 1/RCL,这个极点决定了共源放大电路的带宽。
图3(b)CMOS有源电感并联后的共源放大电路传输函数和低频跨阻增益分别为:
$$ \dfrac{{V}_{out}}{{V}_{in}}(s)=-\dfrac{{g}_{m}}{{g}_{m0}}\dfrac{(1+s{R}_{s}{C}_{gs0})}{{s}^{2}\dfrac{{R}_{s}{C}_{gs0}{C}_{L}}{{g}_{m0}}+s\left(\dfrac{{C}_{L}-{C}_{gs0}}{{g}_{m0}}\right)+1} $$ (4) $$ \frac{{{V_{out}}}}{{{V_{in}}}}(0) = - \frac{{{g_m}}}{{{g_{m0}}}} $$ (5) 共源放大电路传输函数公式(4)中的两个极点为ωcs_p1和ωcs_p2,设ωcs_p1 << ωcs_p2,可计算得其的零极点分别为ωcs_p1 = gm0/(CL−Cgs0),ωcs_p2 = (CL− Cgs0)/ RsCLCgs0,ωcs_z = 1/ Cgs0Rs。
由此可以看出,共源放大电路并联CMOS有源电感后,一方面Cgs0和负载电容CL串联减小了负载电容CL的限制,另一方面为电路系统引入了一对零极点,可以通过调整零点ωcs_z的位置来靠近主极点ωcs_p1减小影响。零点ωcs_z只与电阻Rs和电容Cgs0有关,改变电容Cgs0需要改变晶体管M0的沟道宽度,然而晶体管M0沟道宽度也决定了跨导gm0。因此改变电容Cgs0会影响公式(5)共源放大电路的低频跨阻增益。
文中选择改变电阻Rs来减小零点ωcs_z,靠近主极点ωcs_p1,当电阻Rs满足下列条件公式(6)时,零点ωcs_z和极点ωcs_p1相等,则:
$$ {R_s}{\text{ = }}\frac{{{C_L} - {C_{gs0}}}}{{{g_{m0}}{C_{gs0}}}} $$ (6) 则公式(4)变为极点为ωcs_p2的单极点函数,代入公式(6)极点变为ωcs_p2 = gm0/CL,与电阻负载的共源放大电路公式(3)的单极点ωcs_p0 =1/RCL相比,因为CMOS有源电感中Rs >> 1/gm0,所以ωcs_p2 >> ωcs_p0,共源放大电路的带宽得到提升。
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图4为FCG跨阻放大电路使用CMOS有源电感代替负载电阻R1,R3,与共源放大级并联后的MFCG跨阻放大电路。根据KCL定理得到结点方程,可计算MFCG跨阻放大电路的传输函数为:
$$ \begin{array}{l}{Z}_{TIA}\left(s\right)=\dfrac{{V}_{o}}{{I}_{in}} =\dfrac{\dfrac{{g}_{m1}}{{g}_{m5}{g}_{m6}}\left(s{C}_{gs5}{R}_{1}+1\right)\left(a{s}^{3}+b{s}^{2}+cs+d\right)}{\left({s}^{2}\dfrac{{C}_{o}{C}_{gs5}{R}_{1}}{{g}_{m5}}+s\dfrac{{C}_{o}}{{g}_{m5}}+1\right)\left(s{C}_{in}+G\right)\left(1+s{R}_{2}{C}_{x}\right)\left({s}^{2}\dfrac{{C}_{gs6}{C}_{y}{R}_{3}}{{g}_{m6}}+s\left({C}_{y}+\dfrac{{C}_{gs6}}{{g}_{m6}}\right)+1\right)}\end{array} $$ (7) 式中:
$a = {C_{gs6}}{C_y}{R_3}{R_2}{C_x} $ ;$b = ({R_2}{C_x}({g_{m6}}{C_y} + {C_{gs6}}) + {C_{gs6}}{C_y}{R_3})$ ;$c = ({g_{m6}}{C_y} + {g_{m6}} + {R_2}{C_x}{g_{m6}} - {g_{m2}}{g_{m3}}{R_2}{R_3}{C_{gs6}}) $ ;$d = {g_{m2}}{g_{m3}}{R_2} $ ;$G = {g_{m2}} + \dfrac{1}{{{r_{o1}}}} + \dfrac{1}{{{r_{o2}}}} + \dfrac{1}{{{r_{o4}}}}$ ;${C_{in}} = {C_{pd}} + {C_{ds4}} + {C_{gd4}} + {C_{gs2}} + {C_{ds1}} + {C_{ds2}} + {C_{gs1}}$ ;$ {C_o} = {C_{ds1}} + {C_{gd1}}$ ;${C_x} = {C_{ds2}} + {C_{gd2}} + {C_{gs3}} + {C_{gd3}}$ ;$ {C_y} = {C_{ds3}} + {C_{gd3}} + {C_{gs1}} + {C_{gd1}}$ 。式中:Cdsi ,Cgdi,Cgsi 表示的是晶体管Mi的栅源电容、栅漏电容、漏源电容;1/roi表示的是晶体管Mi的输出电导;上述中i=1,2,3,4,5,6。
由公式(7)分母的极点表达式可以观察到,除了输入结点IN和结点X产生的两个极点外,由于在MFCG跨阻放大电路两级共源放大级使用CMOS有源电感代替了原有的负载电阻,产生了两对分别只与结点Y和结点O有关的极点。根据上一节CMOS有源电感并联共源放大电路的理论分析,通过改变在结点Y处和在结点O处组成CMOS有源电感的电阻R1和R3,使零点靠近较小的极点,从而减小极点对带宽的影响,实现MFCG跨阻放大电路带宽的扩展。
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基于TSMC 60 nm CMOS工艺在Cadence软件平台对图4的MFCG跨阻放大电路进行仿真,其中电源电压为1.8 V,偏置电压Vb为1.1 V,光电二极管结电容设计为Cpd =200 fF,电流源的幅度为Iin=50 μA,电阻R2 =1.5 kΩ,晶体管设计的尺寸参数如表1所示,其中晶体管沟道长度L=60 nm。
表 1 晶体管尺寸
Table 1. Dimnesions of the transistor
M1 M2 M3 M4 M5 M6 W/L 200 66.6 83.3 50 25 66.6 电阻R3从2 kΩ依次增加到5 kΩ,在结点Y的幅频响应,以及电阻R1从4 kΩ依次增加到7 kΩ,在结点O的幅频响应,如图5所示。可以看到,随着电阻R1和R3的增大,结点的带宽也随之增大,但是当电阻R3大于3 kΩ,电阻R1大于5 kΩ时,分别开始出现增益尖峰。因此,将电阻R1设计为5 kΩ,电阻R3设计为3 kΩ,此时,MFCG跨阻放大电路的跨阻增益为55.0 dBΩ,−3 dB带宽为17.2 GHz。此时,放大电路的等效输入噪声电流谱密度如图6所示,由图6可知等效输入噪声电流谱密度在−3 dB带宽内小于55 pA/
$\sqrt{{\rm{Hz}}} $ 。图 5 不同R1在结点O和不同R3在结点Y的幅频响应
Figure 5. Frequency responses of different R1 at node O and different R3 at node Y
MFCG跨阻放大电路的眼图仿真结果如图7所示,在输入20 Gb/s NRZ PBRS31 50 μA的伪随机输入电流时,眼图的垂直张开度为69%和水平张开度为93%,眼图对称完整,能够满足20 Gb/s的光纤通信要求。图8是MFCG跨阻放大电路的版图设计,版图面积为0.0029 mm2,与参考文献[12]使用平面螺旋电感电路的FCG跨阻放大电路版图面积相比,MFCG跨阻放大电路版图面积缩小了71%。
表2为设计的MFCG跨阻放大电路与其他近几年跨阻放大电路的性能比较。可以看出,设计的MFCG跨阻放大电路与参考文献[8]电路相比,虽然在带宽方面相差2.8 GHz,但是电路的增益提高了2.4 dBΩ,版图面积缩小了1255倍。与参考文献[9]电路相比,设计的MFCG跨阻放大电路虽然在增益方面相差4 dBΩ,但是电路的带宽提升了9.3 GHz,版图面积减小了38倍。此外,与参考文献[10-15]相比,设计的MFCG跨阻放大电路在带宽、增益、电路版图面积方面均具有较大的优势。
表 2 性能比较
Table 2. Performace comparison
Ref. Bandwidth/GHz Gain/dBΩ Power/mW Input capacitance/pf Noise current/pA/$\sqrt {{\rm{Hz}}} $ Area/mm2 Technique [8] 20 52.6 1.3 0.05 11 3.64 CASCODE [9] 7.9 59 18 0.3 23 0.11 RGC [10] 7.3 50.5 1 0.2 19.9 \ RGC [11] 9.2 49.7 5.3 0.5 15.3 0.068 RGC [12] 13.4 52.8 2.2 0.32 50 0.01 FCG [13] 6.8 53.9 6.26 0.35 27 0.0064 FCG [14] 3 52 4.3 2 75 0.014 FCG [15] 4 40.6 0.27 0.2 13.7 \ FCG Paper work 17.2 55 3.7 0.2 55 0.0029 FCG
Feedforward common gate transimpedance amplifier circuit based on CMOS active inductor in parallel
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摘要: 设计了一种改进的前馈共栅(Modified Feedforward Common Gate, MFCG)跨阻放大电路,通过使用CMOS有源电感与前馈共栅(Feedforward Common Gate, FCG)跨阻放大电路中的共源放大级并联,使跨阻放大电路的带宽和跨阻增益均得到有效提升。基于TSMC 60 nm CMOS工艺在Cadence软件平台对MFCG跨阻放大电路进行仿真分析和版图设计。仿真结果表明在电源电压为1.8 V,光电二极管结电容为200 fF的情况下,放大电路的−3 dB带宽为17.2 GHz,跨阻增益为55 dBΩ,在带宽内等效输入噪声电流谱密度小于55 pA/
$ \sqrt {{\rm{Hz}}} $ ,电路功耗为3.7 mW,电路版图面积为0.0029 mm2。结果表明:所设计的MFCG跨阻放大电路具有跨阻增益高、带宽大、版图面积小等优点,可用于20 Gb/s光纤通信系统的光接收机电路。Abstract: A modified feedforward common gate transimpedance amplifier circuit was designed. By using CMOS active inductor in parallel with the common source amplifier stage in the feedforward common gate transimpedance amplifier circuit, the bandwidth and gain of the transimpedance amplifier circuit can be improved effectively. Based on TSMC 60 nm CMOS process, simulation analysis and layout design of MFCG cross-resistance amplifier were carried out on Cadence software platform. The simulation results show that when the power supply voltage is 1.8 V and the photodiode junction capacitance is 200 fF, the amplifier circuit's −3 dB bandwidth is 17.2 GHz, the transimpedance gain is 55 dBΩ, the equivalent input noise current spectral density is less than 55 pA /$\sqrt {{\rm{Hz}}} $ in the bandwidth, and the circuit power consumption is 3.7 mW. The circuit layout area is 0.0029 mm2. The results show that the designed MFCG transimpedance amplifier has the advantages of high transimpedance gain, large bandwidth, small layout area and so on, and can be used in the optical receiver circuit of 20 Gb/s fiber communication system. -
表 1 晶体管尺寸
Table 1. Dimnesions of the transistor
M1 M2 M3 M4 M5 M6 W/L 200 66.6 83.3 50 25 66.6 表 2 性能比较
Table 2. Performace comparison
Ref. Bandwidth/GHz Gain/dBΩ Power/mW Input capacitance/pf Noise current/pA/ $\sqrt {{\rm{Hz}}} $ Area/mm2 Technique [8] 20 52.6 1.3 0.05 11 3.64 CASCODE [9] 7.9 59 18 0.3 23 0.11 RGC [10] 7.3 50.5 1 0.2 19.9 \ RGC [11] 9.2 49.7 5.3 0.5 15.3 0.068 RGC [12] 13.4 52.8 2.2 0.32 50 0.01 FCG [13] 6.8 53.9 6.26 0.35 27 0.0064 FCG [14] 3 52 4.3 2 75 0.014 FCG [15] 4 40.6 0.27 0.2 13.7 \ FCG Paper work 17.2 55 3.7 0.2 55 0.0029 FCG -
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