Research progress of excimer laser annealing in semiconductor integrated circuit manufacturing
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摘要: 随着半导体集成电路芯片的尺寸越来越小、结构越来越复杂,芯片制造过程中的退火工艺技术也在不断进步。激光退火以其在芯片制造过程中热预算控制的优势,在芯片制造退火工艺中的重要性正在显现。而准分子激光的特点是波长短、峰值功率高、作用于大多数物质表面时能量迅速被物质表面吸收。准分子激光退火可以实现对材料表面温度梯度的控制,是半导体集成电路制造中热处理工艺的重要选择。对半导体集成电路制造过程中准分子激光退火研究进展进行了综述。概述了集成电路制造中退火工艺热预算控制与激光退火的理论模拟研究结果;着重介绍了准分子激光退火在离子掺杂控制、超浅节形成、沟道外延等材料处理中的研究进展,以及在金属层制备和3D器件中的应用。研究表明,准分子激光退火工艺有望为三维半导体集成电路制造提供新的解决方案。Abstract:
Significance In the dynamic landscape of semiconductor device fabrication, continual advancements strive to enhance the process. As the density of transistors per unit area increases and chip components become progressively smaller, the challenges in chip production grow in both intricacy and difficulty. Traditional methods like furnace annealing are becoming inadequate for the evolving demands of chip manufacturing. To address the intricacies posed by shrinking device sizes, annealing techniques and process parameters undergo constant refinement. Pulsed laser annealing emerges as a noteworthy solution, capable of precisely irradiating specific material areas in extremely brief intervals. This technique, harnessed by absorbing laser energy, rapidly elevates the material surface temperature to induce melting. The consequential reconstruction of the melt layer's crystal structure, coupled with redistributed doping in the crystal, serves the crucial purpose of eliminating defect-activated doping. The excimer laser, operating as a nanosecond pulsed ultraviolet laser, holds distinctive attributes that render it particularly meaningful in semiconductor manufacturing annealing technology. Its short wavelength, narrow pulse width, and minimal material penetration depth, especially in semiconductor materials like silicon, contribute to high absorption rates. Moreover, excimer lasers boast high resolution in focusing or projection, coupled with substantial single-pulse energy. This inherent flexibility allows for shaping the energy distribution of the pulse spot, offering adaptability to diverse requirements. These defining characteristics underscore the significance of excimer laser research in advancing semiconductor manufacturing annealing technologies. Progress To optimize the annealing effect in semiconductor manufacturing, it is crucial to shorten the thermal annealing time window and carefully regulate peak temperatures. Controlling the temperature gradient from the material's surface to its interior is a pivotal consideration in annealing technology. Laser annealing is a superior alternative, offering more precise thermal budget control when compared to other methods, as illustrated in Fig.1. Additionally, the perspective of K. Huet et al. on laser thermal budget is presented. Researchers have explored the application of laser annealing in ion doping and epitaxial layer growth. The evolution of doping concentration across different substrates and dopants under excimer laser conditions has been thoroughly investigated. Brief insights into strain silicon technology and silicon on insulator technology are provided, showcasing their integration into semiconductor manufacturing for enhanced device performance. Excimer lasers have been employed by researchers to delve into devices utilizing strained silicon technology and silicon on insulator technology. In the continuous evolution of semiconductor manufacturing processes, there is ongoing innovation in the metal layer. Laser annealing treatment of the metal layer has garnered increased attention, with the reasons for this emphasis briefly explained. Notably, researchers have scrutinized the annealing of metal layers using excimer lasers. The paragraph concludes by briefly addressing the challenges associated with three-dimensional integrated circuit architecture (refer to Fig.27). Manufacturing three-dimensional integrated circuits poses difficulties, particularly in potential damage to the underlying metal and devices during upper-layer annealing. Excimer lasers have emerged as a research focus to address these challenges and optimize the annealing process for three-dimensional integrated circuits. Conclusions and Prospects Excimer laser annealing stands out as a superior choice when compared to alternative annealing methods, particularly evident in the realm of semiconductor integrated circuit manufacturing. The distinct advantages of excimer laser annealing manifest in its exceptional ability to significantly reduce the thermal budget while enabling precise control over the annealing effect. This accuracy proves pivotal in semiconductor manufacturing processes. Moreover, excimer laser annealing brings noteworthy benefits to the table, including the facilitation of high-density doping with enhanced doping activation efficiency. Its unique capacity to distribute doping atoms more effectively and control junction depth contributes to its prominence in the semiconductor industry. The application of excimer laser annealing on metal layers introduces additional advantages. It effectively augments the grain size of the metal, curbing electron boundary scattering, thereby reducing resistivity. This not only enhances the reliability of the metal but also allows for superior thermal budget control. In the context of three-dimensional integrated circuits, excimer laser technology emerges as a transformative solution. It proves highly adept at reducing the thermal budget, a critical consideration in enhancing device stability within these intricate structures. Furthermore, its promising potential lies in addressing the challenges associated with annealing effects on the dopant distribution of the top layer. Excimer laser annealing, with its multifaceted advantages, thus emerges as a promising and versatile solution for optimizing semiconductor manufacturing processes, particularly in the context of three-dimensional integrated circuits. -
Key words:
- semiconductor manufacturing process /
- thermal budget /
- laser annealing /
- excimer laser
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图 30 层间氧化物和底层氧化物的温度与时间的关系。T1: 上层栅极层的温度,T2: 下层栅极层的温度,T3: 体硅顶部的温度[82]
Figure 30. The relationship between temperature and time of interlayer oxides and underlying oxides. T1: the temperature at the upper grid, T2: the temperature at the lower grid, and T3: the temperature at the top of the bulk silicon[82]
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[1] Razavi Behzad. 模拟CMOS集成电路设计[M]. 陈贵灿, 译. 第2版. 西安: 西安交通大学出版社, 2018: 616-619. [2] Hans-Joachim, Gossmann L, Feng Tao, et al. Reverse diode leakage in spike-annealed ultra-shallowjunctions [J]. MRS Online Proceedings Library (OPL), 2001, 669: J4-J8. doi: https://doi.org/10.1557/PROC-669-J8.4 [3] Felch S, Borland J, Fang Z, et al. Optimized BF3P2 LAD implantation with Si-PAI for shallow, abrupt and high quality p+/n junctions formed using low temperature SPE annealing [C]//Ion Implantation Technology, Proceedings of the 14th International Conference, 2002: 52-55. [4] Borland J O. Low temperature shallow junction formation for 70 nm technology node and beyond [J]. MRS Online Proceedings Library (OPL), 2002, 717: 11. doi: https://doi.org/10.1557/PROC-717-C1.1 [5] Kanemoto Kei, Aharoni Herzl, Ohmi Tadahiro. Ultrashallow and low-leakage p+n junction formation by Plasma Immersion Ion Implantation (PIII) and low-temperature post-implantation annealing [J]. Japanese Journal of Applied Physics, 2001, 40(4): 2706-2711. doi: 10.1143/JJAP.40.2706 [6] Osburn C M, Downey D F, Felch S B, et al. Ultra-shallow junction formation using very low energy B and BF/sub 2/ sources [C]//Proceedings of 11th International Conference on Ion Implantation Technology, 1996: 607-610. [7] Shigeo Onishi, Kenichi Tanaka, Keizo Sakiyama. A new method for evaluating temperature distribution by using Si + + B + implantation [C]//Proceedings of SPIE, 1990, 1189: 83-88. [8] Huet Karim, Mazzamuto Fulvio, Tabata Toshiyuki, et al. Doping of semiconductor devices by laser thermal annealing [J]. Materials Science in Semiconductor Processing, 2017, 62: 92-102. doi: 10.1016/j.mssp.2016.11.008 [9] Murto R, Jones K, Rendon M, et al. Activation and deactivation studies of laser thermal annealed boron, arsenic, phosphorus, and antimony ultra-shallow abrupt junctions [C]//International Conference on Ion Implantation Technology Proceedings. Ion Implantation Technology-2000 (Cat. No. 00EX432), 2000: 155-158. [10] Baeri P, Rimini E. Laser annealing of silicon [J]. Materials Chemistry and Physics, 1996, 46(2): 169-177. [11] Talwar S, Verma G, Weiner K H. Ultra-shallow, abrupt, and highly-activated junctions by low-energy ion implantation and laser annealing[C]//1998 International Conference on Ion Implantation Technology. Proceedings (Cat. No. 98EX144), 1998: 1171-1174. [12] Yu Bin, Wang Yun, Wang Haihong, et al. 70 nm MOSFET with ultra-shallow, abrupt, and super-doped S/D extension implemented by laser thermal process (LTP)[C]//International Electron Devices Meeting 1999. Technical Digest (Cat. No. 99CH36318), 1999: 509-512. [13] Goto K, Yamamoto T, Kubo T, et al. Ultra-low contact resistance for deca-nm MOSFETs by laser annealing [C]//International Electron Devices Meeting 1999. Technical Digest (Cat. No. 99CH36318), 1999: 931-933. [14] Lindfors C D, Jones K S, Law M E, et al. Boron activation during solid phase epitaxial regrowth [J]. MRS Online Proceedings Library (OPL), 2000, 610: B10-B12. [15] Lindsay R, Pawlak B J, Stolk P, et al. Optimisation of junctions formed by solid phase epitaxial regrowth for sub-70 nm CMOS [J]. MRS Online Proceedings Library (OPL), 2002, 717: 21. doi: https://doi.org/10.1557/PROC-717-C2.1 [16] Fung S K H, Huang H T, Cheng S M, et al. 65 nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application [C]//Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004: 92-93. [17] Hervé Besaucèle, Audrey Adnet, François Beau, et al. High energy excimer laser system for nanosecond annealing of semiconductor devices [C]//Proceedings of SPIE, 2019, 11042: 110420S. [18] Talwar S, Verma G, Weiner K H, et al. Laser thermal processing for shallow junction and silicide formation [C]//Proceedings of SPIE, 1998, 3506: 74-81. [19] Felch S B, Downey D F, Arevalo A, et al. Sub-melt laser annealing followed by low-temperature RTP for minimized diffusion [C]//2000 International Conference on Ion Implantation Technology Proceedings. Ion Implantation Technology-2000 (Cat. No. 00EX432), 2000: 167-170. [20] Talwar S, Markle D, Thompson M O. Junction scaling using lasers for thermal annealing [J]. Solid State Technology 2003, 46(7), 83-84, 86, 88. [21] Pouydebasque A, Dumont B, Denorme S, et al. High density and high speed SRAM bit-cells and ring oscillators due to laser annealing for 45 nm bulk CMOS [C]//IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest, 2005: 663-666. [22] Yamamoto T, Kubo T, Sukegawa T, et al. Junction profile engineering with a novel multiple laser spike annealing scheme for 45-nm node high performance and low leakage CMOS technology [C]//2007 IEEE International Electron Devices Meeting, 2007: 143-146. [23] Triyoso D H, Spencer G, Hegde R I, et al. Laser annealed HfxZr1−xO2 high-k dielectric: Impact on morphology, microstructure, and electrical properties [J]. Applied Physics Letters, 2008, 92(11): 113501. doi: 10.1063/1.2898710 [24] Linder B P, Dasgupta A, Ando T, et al. Process optimizations for NBTI/PBTI for future replacement metal gate technologies [C]//2016 IEEE International Reliability Physics Symposium (IRPS), 2016: 1B-4B. [25] Liu Y, Gluschenkov O, Li J, et al. Strained Si channel MOSFETs with embedded silicon carbon formed by solid phase epitaxy [C]//2007 IEEE Symposium on VLSI Technology, 2007: 44-45. [26] Narasimha S, Chang P, Ortolland C, et al. 22 nm high-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned via 15LM BEOL [C]//2012 International Electron Devices Meeting, 2012: 3.3.1-3.3.4. [27] Simões S, Calinas R, Vieira M T, et al. In situ TEM study of grain growth in nanocrystalline copper thin films [J]. Nanotechnology, 2010, 21(14): 145701. doi: 10.1088/0957-4484/21/14/145701 [28] Carta F, Gates S M, Limanov A B, et al. Sequential lateral solidification of silicon thin films on Cu BEOL-integrated wafers for monolithic 3-D integration [J]. IEEE Transactions on Electron Devices, 2015, 62(11): 3887-3891. doi: 10.1109/TED.2015.2479087 [29] Liu Z, Gluschenkov O, Niimi H, et al. Dual beam laser annealing for contact resistance reduction and its impact on VLSI integrated circuit variability [C]//2017 Symposium on VLSI Technology, 2017: T212-T213. [30] Liu W H, Luo J W, Li S S, et al. The seeds and homogeneous nucleation of photoinduced nonthermal melting in semiconductors due to self-amplified local dynamic instability [J]. Science Advances, 2022, 8(27): eabn4430. doi: 10.1126/sciadv.abn4430 [31] Sundaram S K, Mazur E. Inducing and probing non-thermal transitions in semiconductors using femtosecond laser pulses [J]. Nature Materials, 2002, 1(4): 217-224. doi: 10.1038/nmat767 [32] Lee C, Srisungsitthisunti P, Park S, et al. Control of current saturation and threshold voltage shift in indium oxide nanowire transistors with femtosecond laser annealing [J]. Acs Nano, 2011, 5(2): 1095-1101. doi: 10.1021/nn102723w [33] Smith M J, Lin Y T, Sher M J, et al. Pressure-induced phase transformations during femtosecond-laser doping of silicon [J]. Journal of Applied Physics, 2011, 110(5): 053524. [34] Chen C, Chen G, Yang H, et al. Solution-processed metal oxide arrays using femtosecond laser ablation and annealing for thin-film transistors [J]. Journal of Materials Chemistry C, 2017, 5(36): 9273-9280. doi: 10.1039/C7TC01953J [35] Frank M M, Cartier E A, Lavoie C, et al. Crystallization of hafnium-oxide-based ferroelectrics for BEOL integration [C]//2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM). IEEE, 2022: 316-318. [36] Bayer L, Ye X, Lorenz P, et al. Studies on perovskite film ablation and scribing with ns-, ps-and fs-laser pulses [J]. Applied Physics A, 2017, 123: 1-8. doi: 10.1007/s00339-016-0611-9 [37] 刘敏, 郑柳, 何志等. 硅晶圆中注入10 MeV磷的连续激光退火激活[J]. 激光与红外, 2022, 52(07): 1000-1003. doi: 10.3969/j.issn.1001-5078.2022.07.008 Liu Min, Zheng Liu, He Zhi, et al. Continuous laser annealing for activating 10 MeV implanted phosphorus in silicon wafer [J]. Laser & Infrared, 2022, 52(7): 1000-1003. (in Chinese) doi: 10.3969/j.issn.1001-5078.2022.07.008 [38] 王怡哲, 喻学昊, 刘墨林等. 低抖动准分子激光放大器光源的研究[J]. 红外与激光工程, 2023, 52(03): 170-176. Wang Yizhe, Yu Xuehao, Liu Molin, et al. Study on light source of low jitter excimer laser amplifier [J]. Infrared and Laser Engineering, 2023, 52(3): 20220468. (in Chinese) [39] Scott J C, Gluschenkov O, Goplen B, et al. Reduction of RTA-driven intra-die variation via model-based layout optimization [C]//2009 Symposium on VLSI Technology, 2009: 152-153. [40] Miyashita T, Kubo T, Kim Y S, et al. A study on millisecond annealing (MSA) induced layout dependence for flash lamp annealing (FLA) and laser spike annealing (LSA) in multiple MSA scheme with 45 nm high-performance technology [C]//2009 IEEE International Electron Devices Meeting (IEDM), 2009: 1-4. [41] Huet Karim, Tabata Toshiyuki, Aubin Joris, et al. Laser thermal annealing for low thermal budget applications: from contact formation to material modification (invited) [J]. ECS Transactions, 2019, 89(3): 137. doi: 10.1149/08903.0137ecst [42] Lombardo S F, Fisicaro G, Deretzis I, et al. Theoretical study of the laser annealing process in FinFET structures [J]. Applied Surface Science, 2019, 467-468: 666-672. doi: 10.1016/j.apsusc.2018.10.155 [43] Dagault L, Kerdilès S, Acosta A P, et al. Investigation of recrystallization and stress relaxation in nanosecond laser annealed Si1−xGex/Si epilayers [J]. Applied Surface Science, 2020, 527: 146752. doi: 10.1016/j.apsusc.2020.146752 [44] Ni C N, Rao K V, Khaja F, et al. Ultra-low NMOS contact resistivity using a novel plasma-based DSS implant and laser anneal for post 7 nm nodes [C]//2016 IEEE Symposium on VLSI Technology, 2016: 1-2. [45] Tabata T, Aubin J, Huet K, et al. Super activation of highly surface segregated dopants in high Ge content SiGe obtained by melt UV laser annealing [C]//22nd International Conference on Ion Implantation Technology (IIT), 2018: 353-356. [46] Tabata T, Aubin J, Huet K, et al. Impact of solidification velocity on activation of Ga, In, and Al segregated in high Ge content SiGe by UV melt laser anneal [C]//2019 Electron Devices Technology and Manufacturing Conference (EDTM), 2019: 130-132. [47] Tabata Toshiyuki, Aubin Joris, Huet Karim, et al. Segregation and activation of Ga in high Ge content SiGe by UV melt laser anneal [J]. Journal of Applied Physics, 2019, 125(21): 215702. doi: 10.1063/1.5096889 [48] Everaert J L, Schaekers M, Yu H, et al. Sub-10−9 Ω·cm2 contact resistivity on p-SiGe achieved by Ga doping and nanosecond laser activation [C]//2017 Symposium on VLSI Technology, 2017: T214-T215. [49] Yu H, Wang L L, Schaekers M, et al. Lanthanum and lanthanum silicide contacts on N-type silicon [J]. IEEE Electron Device Letters, 2017, 38(7): 843-846. doi: 10.1109/LED.2017.2700233 [50] Yu H, Schaekers M, Schram T, et al. Multiring circular transmission line model for ultralow contact resistivity extraction [J]. IEEE Electron Device Letters, 2015, 36(6): 600-602. doi: 10.1109/LED.2015.2425792 [51] Li C I, Breil N, Wen T Y, et al. p-type MOSFET contact resistance improvement by conformal plasma doping and nanosecond laser annealing [J]. IEEE Electron Device Letters, 2019, 40(2): 307-309. doi: 10.1109/LED.2019.2890950 [52] van Dal M J H, Vellianitis G, Doornbos G, et al. Ge CMOS gate stack and contact development for Vertically Stacked Lateral Nanowire FETs[C]//2018 IEEE International Electron Devices Meeting (IEDM), 2018: 21.1.1-21.1.4. [53] Wang Z, Mingo N. Diameter dependence of SiGe nanowire thermal conductivity [J]. Applied Physics Letters, 2010, 97(10): 101903. doi: 10.1063/1.3486171 [54] Mingo Natalio, Yang Liu, Li Deyu, et al. Predicting the thermal conductivity of Si and Ge nanowires [J]. Nano Letters, 2003, 3(12): 1713-1716. doi: 10.1021/nl034721i [55] Hung R, Khaja F A, Hollar K E, et al. Novel solutions to enable contact resistivity <1E-9 Ω-cm2 for 5 nm node and beyond [C]//2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2018: 1-2. [56] Lee R T P, Petrov N, Kassim J, et al. Nanosecond laser anneal for BEOL performance boost in advanced FinFETs[C]//2018 IEEE Symposium on VLSI Technology, 2018: 61-62. [57] Batude P, Fenouillet-Beranger C, Pasini L, et al. 3 DVLSI with CoolCube process: An alternative path to scaling [C]//2015 Symposium on VLSI Technology (VLSI Technology), 2015: T48-T49. [58] Fenouillet-Beranger C, Batude P, Brunet L, et al. Recent advances in 3D VLSI integration [C]//2016 International Conference on IC Design and Technology (ICICDT), 2016: 1-4. [59] Bosch D, Alba P A, Kerdiles S, et al. Laser processing for 3D junctionless transistor fabrication [C]//2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2019: 1-3. [60] Derakhshandeh J, Tajari Mofrad M R, Ishihara R, et al. A study of the CMP effect on the quality of thin silicon films crystallized by using the μ-Czochralski process [J]. Journal of the Korean Physical Society, 2009(54): 432-436. [61] Ishihara R, van der Wilt P C, van Dijk B D, et al. Location-control of large grains by μ-czochralski (grain filter) process and its application to single-crystalline silicon thin-film transistors [J]. Thin Solid Films, 2003, 427(1-2): 77-85. [62] Lisoni J G, Arreghini A, Congedo G, et al. Laser thermal anneal of polysilicon channel to boost 3D memory performance [C]//2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014: 1-2. [63] Huet K, Boniface C, Negru R, et al. Ultra low thermal budget anneals for 3D memories: Access device formation [J]. AIP Conference Proceedings, 2012, 1496(1): 135-138. [64] Congedo G, Arreghini A, Liu L, et al. Analysis of performance/variability trade-off in Macaroni-type 3-D NAND memory [C]//2014 IEEE 6th International Memory Workshop (IMW), 2014: 1-4. [65] La Magna Antonino, Alippi Paola, Privitera Vittorio, et al. A phase-field approach to the simulation of the excimer laser annealing process in Si [J]. Journal of Applied Physics, 2004, 95(9): 4806-4814. doi: 10.1063/1.1690861 [66] Fortunato G, Mariucci L, Stanizzi M, et al. Ultra-shallow junction formation by excimer laser annealing and low energy (<1 keV) B implantation: A two-dimensional analysis [J]. Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, 2002, 186(1): 401-408. [67] Chong Y F, Pey K L, Wee A T S, et al. Annealing of ultrashallow p+/n junction by 248 nm excimer laser and rapid thermal processing with different preamorphization depths [J]. Applied Physics Letters, 2000, 76(22): 3197-3199. doi: 10.1063/1.126627 [68] Do Seungloo, Kong Seong, Lee Yonglyun, et al. Ultra-shallow junction formation using plasma doping and excimer laser annealing for nano-technology CMOS applications [J]. Journal of the Korean Physical Society, 2009, 55: 1065-1069. doi: 10.3938/jkps.55.1065 [69] Aid S R, Rashid N N M, Jonny N F A, et al. Preliminary study on laser annealed NP Junction in phosphorus implanted germanium [C]//2020 IEEE International Conference on Semiconductor Electronics (ICSE). IEEE, 2020: 152-155. [70] Tabata T, Raynal P E, Huet K, et al. Segregation and activation of Sb implanted in Si by UV nanosecond-laser-anneal-induced non-equilibrium solidification[J]. Journal of Applied Physics, 2020, 127(13): 135701. [71] Kim Seong-Dong, Park Cheol-Min, Woo J C S. Advanced source/drain engineering for box-shaped ultrashallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOI CMOS [J]. IEEE Transactions on Electron Devices, 2002, 49(10): 1748-1754. doi: 10.1109/TED.2002.803634 [72] Chery N, Zhang M, Monflier R, et al. Study of recrystallization and activation processes in thin and highly doped silicon-on-insulator layers by nanosecond laser thermal annealing [J]. Journal of Applied Physics, 2022, 131(6): 65301. doi: 10.1063/5.0073827 [73] Borland J, Qin S, Oesterlin P, et al. High mobility Ge-channel formation by localized/selective liquid phase epitaxy (LPE) using Ge+B plasma ion implantation and laser melt annealing [C]//2013 13th International Workshop on Junction Technology (IWJT), 2013: 49-53. [74] Ong C Y, Pey K L, Li X, et al. Laser annealing induced high Ge concentration epitaxial SiGe layer in Si1−xGex virtual substrate [J]. Applied Physics Letters, 2008, 93(4): 41112. doi: 10.1063/1.2962991 [75] Dagault L, Acosta-Alba P, Kerdiles S, et al. Impact of UV nanosecond laser annealing on composition and strain of undoped Si0.8Ge0.2 epitaxial layers [J]. ECS Journal of Solid State Science and Technology, 2019, 8: 202-208. doi: 10.1149/2.0191903jss [76] Karmous I, Rozé F, Raynal P E, et al. Non-equilibrium growth of surface wrinkles emerging in an SiO2/Si stack during Si melting induced by UV nanosecond pulsed laser annealing [J]. ECS Journal of Solid State Science and Technology, 2022, 11(10): 104006. doi: 10.1149/2162-8777/ac9beb [77] Fenouillet-Beranger C, Acosta-Alba P, Mathieu B, et al. Ns laser annealing for junction activation preserving inter-tier interconnections stability within a 3D sequential integration [C]//2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016: 1-2. [78] Jourdan N, Roze F, Tabata T, et al. UV nanosecond laser annealing for Ru interconnects [C]//2020 IEEE International Interconnect Technology Conference (IITC), 2020: 163-165. [79] Usami Y, Imokawa K, Nohdomi R, et al. Change in resistivity of fine metal line by KrF excimer laser annealing [C]//2022 IEEE International Interconnect Technology Conference (IITC), 2022: 108-110. [80] Rajendran B, Jain S H, Kramer T A, et al. Thermal simulation of laser annealing for 3D integration [C]//Proceedings VMIC, 2003: 1-6. [81] Vandooren A, Wu Z, Parihar N, et al. 3D sequential low temperature top tier devices using dopant activation with excimer laser anneal and strained silicon as performance boosters [C]//2020 IEEE Symposium on VLSI Technology, 2020: 1-2. [82] Fenouillet-Beranger C, Mathieu B, Previtali B, et al. New insights on bottom layer thermal stability and laser annealing promises for high performance 3D VLSI [C]//2014 IEEE International Electron Devices Meeting, 2014: 25-27. [83] Cavalcante C, Fenouillet-Beranger C, Batude P, et al. 28 nm FDSOI CMOS technology (FEOL and BEOL) thermal stability for 3D sequential integration: yield and reliability analysis [C]//2020 IEEE Symposium on VLSI Technology, 2020: 1-2. [84] Lisoni J G, Arreghini A, Congedo G, et al. Laser thermal annealneal of polysilicon channel to boost 3D memory performance [C]//2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014: 1-2. [85] Congedo G, Arreghini A, Liu L, et al. Analysis of perfor-mance/variability trade-off in Macaroni-type 3-D NAND memory [C]//2014 IEEE 6th International Memory Workshop (IMW), 2014: 1-4.