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所设计的1280 × 1024, 10 μm数字焦平面读出电路基于0.18 μm标准CMOS工艺进行了实现,图8为读出电路的芯片照片,所设计的数字读出电路与短波红外探测器进行了倒装焊互连,实现了数字短波红外探测器,其照片如图9所示。基于自主开发的测试平台对所设计的读出电路进行了测试。
在无光电流输入的情况下,对读出电路进行200帧输出数据的采集,通过计算每个像元的RMS噪声并计算所有像元RMS噪声的平均值,最终得到整个读出电路的读出噪声为1.03 LSB(最小可分辨位数),约为157 μV,测试结果如图10所示。
同样在无光电流输入的情况下,对读出电路输出数据求各列的平均值,并计算各列平均值的RMS值,最终得到读出电路的列FPN为18.5 LSB,约为整个输出范围的0.1%。得益于对ADC阵列采用的失调消除设计,相比参考文献[6]的设计,列FPN改善了约60%,测试结果如图11所示。
Figure 11. (a) Proposed 1280 × 1024, 10 μm DROIC’s column FPN test result; (b) Column FPN test result of 640 × 512, 15 μm DROIC mentioned in Ref. [6]
在50 Hz帧频的条件下,对读出电路的功耗进行了测试,其工作电压为3.3 V(像元阵列和ADC阵列等模块的工作电压)和1.8 V(数据传输和逻辑控制电路等模块的工作电压),测得读出电路的总功耗为165 mW,其中读出单元阵列的功耗为70 mW,ADC阵列的功耗为68 mW,4通道数据传输电路的功耗为17 mW,其余电路模块(包括逻辑控制电路和偏置电流产生电路等)的功耗为10 mW,如图12所示。
表1统计了所设计的数字读出电路的性能指标并与国外同类产品进行了比较。所设计的数字读出电路在ADC位数和噪声等性能指标方面达到国外产品的水平,但功耗和帧频还有改进的空间。ADC的转换速度是制约读出电路工作速度的关键因素之一,此外从图12可以看到,ADC阵列的功耗占整个读出电路功耗的40%以上,因此可以采用低功耗、高速列级ADC结构改善读出电路的功耗和工作速度,例如三阶Incremental Sigma-Delta ADC结构,其完成一次转换所需的时钟个数相比文中所采用的二阶Incremental Sigma-Delta ADC可以降低约3.5倍,不仅可以支持更高帧频的应用,而且数字模块的功耗可以大大降低;从图12还可以看到,读出单元阵列的功耗也是读出电路功耗的主要组成部分,因此低功耗CTIA注入级电路设计也是项目组下一步的研究方向之一。
Parameter This work SCD cardinal 1 280 HD [10] SBF262 [4] Format 1280 × 1024 1280 × 1024 1280 × 1024 Pitch/μm 10 10 16 Reading mode IWR/ITR IWR/ITR IWR/ITR ADC/bit 14 13 22 Well capacity 750 ke− 500 ke−
(Medium gain)−450 ke− Noise 59 e− 170 e− 93 e− Frame rate (max)/Hz 100 160 200 Power consumption 165 mW
@ 50 Hz150 mW
@ 60 Hz— Power supply/V 3.3/ 1.8 3.3/ 1.8 — Table 1. Comparison of performance between different DROICs
所设计的数字读出电路与短波红外探测器进行了倒装焊互连,实现了数字短波红外探测器组件,并搭配光学镜头和简易工装进行了成像验证,图13和图14为成像效果,图像经过了简单的两点校正。可以看到图像细节丰富,由于数字化探测器较好的信噪比和抗干扰性,成像清晰无杂波干扰。
1280 × 1024, 10 μm digital IRFPA readout integrated circuit design (Invited)
doi: 10.3788/IRLA20211113
- Received Date: 2021-12-25
- Rev Recd Date: 2022-02-10
- Publish Date: 2022-05-06
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Key words:
- IRFPA /
- digital ROIC /
- large format /
- small pixel /
- column level ADC
Abstract: Digital readout of infrared focal plane array (IRFPA) orients its development. Compared with traditional analog IRFPA, digital IRFPA has many advantages. The critical technique of digital IRFPA is the digital readout integrated circuit (DROIC). The design and implementation of the 1280 × 1024, 10 μm DROIC was introduced in detail in this paper. The DROIC was tested and the results showed its noise was 157 μV, the power consumption was 165 mW when frame rate was 50 Hz, and the column fix pattern noise was 0.1%. The DROIC interconnected short-wave infrared detector through flip chip successfully and completed imaging. The images had good resolution and rich details. The test results and images’ effect indicated that the DROIC has some features, such as low noise, wide transmission bandwidth and good resistance to interference and so on, and contributes to the development of IRFPA’s performance.