IRFPA ROIC integrated digital output

Gao Lei; Zhai Yongcheng; Liang Qinghua; Jiang Dazhao; Ding Ruijun

In order to achieve infrared focal plane digital output, an IRFPA readout circuit integrated on-chip ADC was designed, including a 512512 cell array readout circuit and shared the successive approximation register analog to digital converters(SAR ADC). Unit readout circuit using direct injection (DI) structure as the input stage, the output signal was sent through the multiplexes to ADC. The comparator designed in successive approximation ADC was a high-speed comparator which consisted of the preamplifier, latches, self-biasing differential amplifiers and output drives. The digital to analog converter (DAC) used a three-stage structure which the charge scaling was combined of voltage scaling. Using the Cadence and Synopsys design platform for circuit's design, simulation and layout design. The circuit was taped out by GLOBALFOUNDRIES company using 0.35 m, 3.3 V CMOS process. Test results show the number of significant digits of ADC is 8.2 bit, converts frequency is 150 k Samples/s, power consumption less than 300 W and meet the needs of focal plane 100 frame rates as well as low power consumption.

1. Key Laboratory of Infrared Imaging Materials and Detectors,Shanghai Institute of Technical Physics,Chinese Academy of Sciences,Shanghai 200083,China;

2. University of Chinese Academy of Sciences,Beijing 100049,China

Received Date: 2014-10-14

Rev Recd Date: 2014-11-23

Publish Date: 2015-06-25

Key words:

IRFPA /
ROIC /
on-chip ADC /
SAR /
DAC

Abstract: In order to achieve infrared focal plane digital output, an IRFPA readout circuit integrated on-chip ADC was designed, including a 512512 cell array readout circuit and shared the successive approximation register analog to digital converters(SAR ADC). Unit readout circuit using direct injection (DI) structure as the input stage, the output signal was sent through the multiplexes to ADC. The comparator designed in successive approximation ADC was a high-speed comparator which consisted of the preamplifier, latches, self-biasing differential amplifiers and output drives. The digital to analog converter (DAC) used a three-stage structure which the charge scaling was combined of voltage scaling. Using the Cadence and Synopsys design platform for circuit's design, simulation and layout design. The circuit was taped out by GLOBALFOUNDRIES company using 0.35 m, 3.3 V CMOS process. Test results show the number of significant digits of ADC is 8.2 bit, converts frequency is 150 k Samples/s, power consumption less than 300 W and meet the needs of focal plane 100 frame rates as well as low power consumption.

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Reference (15)

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IRFPA ROIC integrated digital output

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